The invention relates generally to integrated circuits and, more particularly, to capacitor structures for use therein.
There is an ongoing need in the integrated circuit (IC) industry for high performance capacitors. This need is particularly strong in the area of digital processing devices (e.g., microprocessors). For example, as the performance levels of digital processing devices continue to rise, there is an increasing need for capacitor structures that are capable of performing de-coupling functions for these high speed devices. Such de-coupling capacitors are often called upon to provide high di/dt (i.e., high-rate current change) operation for these processing devices. In the past, conventional capacitor structures (e.g., parallel plate capacitors) were often implemented on the IC package to provide de-coupling capacitance within the device. It is anticipated, however, that these conventional capacitor structures will not be capable of providing the performance levels required by next generation digital processing devices.
In a more recent approach, de-coupling capacitor structures have been implemented on the back of the silicon die. However, such techniques have proven difficult to implement. For example, the high temperature anneal process required by many of the high dielectric constant insulating materials used in such capacitors will often create problems when attempting to meet the allowable thermal budget associated with a process. Techniques have also been proposed for building up layers on the microprocessor chip to provide the de-coupling structures. However, these techniques can also present thermal budget problems when high dielectric constant insulating materials are used. In addition, these techniques will often require a relatively large number of alternating layers to achieve the required capacitance. A number of architectural de-coupling approaches have also been proposed and implemented including, for example, techniques involving clock throttling and microcode changes. These architectural solutions, however, can result in significant reductions in performance within a processor.